1. Field of the Invention
The present invention relates to improving the operation of analog-to-digital converters ("ADCs"). More specifically, it relates to the removal of clock noise from the sampling process, thereby improving the resolution of the ADC.
2. Description of the Related Art
When digital processing hardware receives an analog signal, it first digitizes the analog signal with an analog-to-digital converter (ADC). After the signal has been digitized, it may be forwarded to downstream digital processing circuitry for further analysis and/or manipulation. Not surprisingly, in many applications, it is desirable to use an inexpensive ADC which produces high resolution digital samples at a relatively high rate.
Currently, several different types of ADCs are used in the art. This nonexclusive list includes successive approximation ADCs, dual slope integrating ADCs, and charge balancing ADCs.
Successive approximation ADCs provide a fast analog-to-digital conversion of a momentary value of the analog input signal. Generally, they work by first comparing the sampled input voltage with a voltage that is one-half the input range. If the sampled input voltage is greater, the ADC then compares the sampled input signal with three-quarters of the input range, and so on. For example, twelve such steps provides twelve-bit resolution. While these successive comparisons are taking place, the signal is frozen in a sample and hold circuit. After conversion, the resulting bytes are typically placed into either a pipeline or buffer store.
Dual slope integrating ADCs operate a bit differently. Integrating ADCs let the analog input signal charge a capacitor for a fixed period of time. The converter then measures the time required for the capacitor to fully discharge at a fixed rate. This time is a measure of the integrated input voltage.
Charge balancing ADCs simultaneously charge and discharge a capacitor. That is, a capacitor is charged with an input analog signal for a fixed period of time only to then be discharged in discrete units called charge packets. If the capacitor is charged to more than the packet size it will release a packet (i.e., through discharging). On the contrary, if the capacitor is not charged to more than the packet size, a packet will not be released. This systematic and simultaneous charging and discharging of the capacitor, which results in the release of charge packets, produces a pulse train. The input voltage is determined, and, hence, the digital signal is formed, by counting the packets released by the capacitor (i.e., the pulse train).
FIG. 1 depicts a block diagram of a successive approximation ADC similar to that currently being used on the Lucent Technologies, Inc. "1615/POMP15" digital signal processor chip. A sample and hold circuit 23 is coupled to a non-overlap generator 22. The non-overlap generator 22 is, in turn, coupled to one stage of a rotating ones counter 10; each stage of the counter 10 receiving clock pulses from the ADC clock ADCCLK.
An analog input signal 60 is fed into the sample and hold circuit 23. The sample and hold circuit 23, as is well known in the art, actually performs the reading and recording of the sampled analog signal. That is, the circuit 23 includes a capacitor which records the amplitude level of the sampled signal as a charging voltage level, during the period when the SAMPLE signal is enabled. Thereafter, the SAMPLE signal is disabled and the HOLD circuit is enabled, wherein the actual evaluation of the analog signal takes place, much like that described above for successive approximation ADCs.
The non-overlap generator 22 acts as a task manager, ensuring that the sampling function and the holding function, of the sample and hold circuit 23, do not overlap. Thereafter, the voltage sample 59 is input to an analog-to-digital x-bit counter 56 for digitizing, where x designates the degree of resolution (e.g., 12-bit). The digitized signal is then typically stored or buffered in a parallel latch 57 until it is needed.
The resulting x-bit digital word 48 contains a weighting hierarchy, wherein d.sub.0 is called the least significant bit because it represents the smallest weighting and d.sub.x-1 is called the most significant bit since it represents the largest weighting.
Also depicted in FIG. 1 is the PLL circuit 14 from which the ADC clock ADCCLK is ordinarily derived. A voltage controlled oscillator ("VCO") 15, running at a very high frequency VCOCLK is divided down by a factor of J within divider circuitry 16, forming the ADC clock ADCCLK. The ADC clock is then forwarded to the rotating ones counter 10 for controlling the enabling of the SAMPLE signal, via the output of one stage of the counter 10, and for controlling the successive approximation algorithm.
The frequency of the ADC clock ADCCLK is maintained relatively constant by the PLL circuit 14, wherein the ADC clock ADCCLK (which is also the VCO clock/J) is further divided down by a factor of K, forming the reference clock 27. The reference clock 27 (i.e., also equal to the VCO clock/(J)(K)) is then fed into a phase detector circuit 13 for comparison to a lower frequency oscillator clock KOSC, where the reference clock 27 is desired to be equal to KOSC. After detecting the phase difference (if any) between the oscillator clock KOSC and the reference clock 27, the phase detector sends a voltage control signal 25 through a loop filter 14. After having been filtered, the filtered voltage control signal 26 is sent to the VCO 15, providing an increased, or decreased voltage, whereby the clock frequency of the VCO 15 is adjusted either up or down, or not at all. The desired result is for the VCOCLK to be maintained at a frequency level equal to KOSC.times.J.times.K.
The PLL attempts to maintain the ADC clock ADCCLK at a frequency equal to the low frequency oscillator clock frequency KOSC multiplied by a factor K, where the ADC clock ADCCLK is sufficiently faster than the low frequency KOSC to enable the ADC to efficiently carry out the successive approximation process.
Notwithstanding the efforts of the PLL circuit 14 to so regulate the ADC clock ADCCLK, noise invariably enters the system and adversely affects the regularity of the ADC clock's clock frequency ADCCLK.
One specific example of an element of noise which can easily be introduced into the PLL circuit 14 is that of thermal noise. Thermal noise is defined as kTRB, where k is Boltzmann's constant, T is the temperature, R is the circuit impedance, and B is the oscillation bandwidth; the only variable being the temperature (T). Hence, thermal noise, and its concomitant effects, increase proportionally with the temperature.
Another source of clock noise is due to the fact that ordinarily, the PLL circuit 14 is designed to operate on as low a power level as possible (e.g., the "1615/POMP15" is driven by a 38.4kHz clock which is multiplied up to several tens of MHz), thus requiring very high internal impedance values at various nodes throughout the PLL circuit 14. As is well known in the art, the higher the internal impedance of the PLL circuit 14, the more susceptible it is to noise. The susceptibility phenomenon is exacerbated in those instances in which the PLL circuit 14 is not securely tied to ground, as in a floating configuration.
One specific manifestation of noise being introduced within the PLL circuit 14 is clock pulse "jitter." Jitter, as it in known in the art, relates to the non-fixed frequency of the clock pulse used to drive the sampling and conversion processes; in this case, the ADC clock ADCCLK If the frequency of the ADC clock ADCCLK is not precisely fixed, it may cause serious operational problems for the ADC, reducing accuracy and resolution.
More specifically, when the ADC clock ADCCLK frequency is not fixed during the sampling process, the portion of the signal being sampled varies with the frequency, thus resulting in a tainted evaluation of the analog signal. That is, during the sampling process, a first clock pulse from the noisy ADC clock ADCCLK instructs the ADC to begin sampling the analog signal. The ADC will continue sampling the analog signal until it receives a pre-determined number of additional clock pulses from the noisy ADC clock ADCCLK In as much as it is the exact point in time when the sampling is stopped that determines which portion of the analog signal has been sampled, the accuracy and precise timeliness of the arrival of that "disabling" clock pulse ADCCLK directly affects the accuracy of the ADC and the resolution of the digitized signal.
Still referring to FIG. 1, a rotating ones counter 10 configured with successively coupled D flip-flops FF1, FF2, . . . FFn, such as in use within the digital control logic of a successive approximation ADC, is shown. As is well known in the art, counters (such as the rotating ones counter 10) are found in almost all equipment containing digital logic. They are used for counting the number of occurrences of an event and for generating timing sequences to control various digital operations, such as the enabling and disabling of a SAMPLE signal.
As it is used in FIG. 1, the counter 10 performs two primary functions within the ADC that are most relevant to the present invention: i) initiating the sampling process by enabling the SAMPLE signal upon a first clock pulse, and ii) ending the sampling process by disabling the SAMPLE signal upon sending a second clock pulse some time after the first clock pulse.
In as much as the rotating ones counter 10 is driven by the noisy ADC clock ADCCLK, the ADC clock ADCCLK jitter has an effect upon the timing of the counter 10 that is perpetuated throughout the ADC system. Specifically, of the counter's 10 two most relevant functions, the one function affected most adversely is that of disabling the sampling signal SAMPLE since, as previously mentioned, it is the instant at which sampling stops that determines the portion of the analog signal that has been sampled.
Furthermore, in as much as the counter 10 controls the analog-to-digital conversion process, any jitter present within the ADC clock pulse ADCCLK will result in the jitter actually modulating the analog signal that is being held on the capacitor within the sample and hold circuitry. This modulation worsens as the sampling frequency increases, thus adding to the adverse affects of the sampling noise.